PCF85263ATLSLASHA datasheet(68/100 Pages) NXP

68 / 100 page

PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

68 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

Figure 36 shows the waveforms that can be expected. sample clock, vdd_int and stop are

internal nodes. vdd_int is the supply which operates the IC and will be either VDD or VBAT,

depending on the state of the battery switch-over.

• At and before t1, SW1 is open (TS pin floating). The TS pin is sampled and the

internal pull-up resistor will pull the pin HIGH to vdd_int. No actions are taken by the

IC.

• At t2, SW1 is still open. No action is taken by the IC.

• At t3, SW1 closes. The TS pin is now shorted to VSS. The TS pin has not been

sampled yet, so no action is taken by the IC.

• At t4, SW1 is closed. The internal pull-up resistor is enabled, but TS pin remains

LOW. The pin is then sampled and the LOW level detected. As the TSL bit was set for

active LOW detection, the HIGH-LOW transition of TS pin sampled triggers an event.

STOPM mode was configured to allow the TS pin to stop the time counting. As the

TSL bit was set for active LOW, time counting stops when the TS pin is LOW.

Timestamp register 2 was configured to take a copy of the time on an event of the TS

pin, hence TSR2 loads the time t4. TSR2F is also set.

Table 66.

Application configuration

Section

Bit(s)

State

Comment

Pin_IO

Section 8.12

TSPM[1:0]

TS pin in input mode

Pin_IO

Section 8.12

TSIM

select mechanical switch mode

Pin_IO

Section 8.12

TSL

TS pin input is active LOW

Function

Section 8.13

STOPM

allow TS pin to control STOP

TSRIEA

allow timestamps to create interrupts

ILPA

generate interrupt pulses

TSR_mode

Section 8.12

TSR2M[2:0]

101

last event mode for timestamp2

Pin_IO

Section 8.12

INTAPM[1:0]

output interrupt on INTA

Fig 36. Application example timing

PCF85263ATL/A Datasheet(PDF) 68 Page - NXP Semiconductors

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