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PCF85263ATL/A Datasheet(PDF) 33 Page - NXP Semiconductors |
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PCF85263ATL/A Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 100 page  PCF85263A All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4.1 — 27 November 2015 33 of 100 NXP Semiconductors PCF85263A Tiny RTC with alarm, battery switch-over, and I2C-bus 8.7.1 Timestamps interrupts The generation of interrupts from the timestamp functions is controlled via the timestamp interrupt enable bits; TSRIEA and TSRIEB. These bits are in registers INTA_enable (address 29h) and INTB_enable (address 2Ah). The loading of new information into one of the timestamp registers can be used to generate an interrupt at pins INTA and INTB. The interrupt may be generated as a pulsed signal every time a timestamp register updates or as a permanently active signal which follows the condition of timestamp flags, TSR1F to TSR3F. The timestamp flags remain set until cleared by command. When enabled, interrupts are triggered every time a timestamp register updates and even if the associated flag is not cleared, an interrupt pulse can be generated. See Section 8.9 on page 38 for interrupt control. Table 22. Timestamp registers in stop-watch mode (RTCM = 1) Bit positions labeled as - are not implemented and return 0 when read. Address Register name Upper-digit (ten’s place) Digit (unit place) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Stop-watch timestamp1 (TSR1) 11h TSR1_seconds - 0 to 5 0 to 9 12h TSR1_minutes - 0 to 5 0 to 9 13h TSR1_hr_xx_xx_00 0 to 9 0 to 9 14h TSR1_hr_xx_00_xx 0 to 9 0 to 9 15h TSR1_hr_00_xx_xx 0 to 9 0 to 9 16h not used -- -- -- -- Stop-watch timestamp2 (TSR2) 17h TSR2_seconds - 0 to 5 0 to 9 18h TSR2_minutes - 0 to 5 0 to 9 19h TSR2_hr_xx_xx_00 0 to 9 0 to 9 1Ah TSR2_hr_xx_00_xx 0 to 9 0 to 9 1Bh TSR2_hr_00_xx_xx 0 to 9 0 to 9 1Ch not used -- -- -- -- Stop-watch timestamp3 (TSR3) 1Dh TSR3_seconds - 0 to 5 0 to 9 1Eh TSR3_minutes - 0 to 5 0 to 9 1Fh TSR3_hr_xx_xx_00 0 to 9 0 to 9 20h TSR3_hr_xx_00_xx 0 to 9 0 to 9 21h TSR3_hr_00_xx_xx 0 to 9 0 to 9 22h not used -- -- -- -- |
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