PCF85263ATLSLASHA datasheet(64/100 Pages) NXP

64 / 100 page

PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

64 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

9.2 START and STOP conditions

A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START

condition - S.

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition - P (see Figure 34).

9.3 Acknowledge

Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as

logic 0. A not-acknowledge is defined as logic 1.

When written to, the slave will generate an acknowledge after the reception of each byte.

After the acknowledge, another byte may be transmitted. It is also possible to send a

STOP or START condition.

When read from, the master receiver must generate an acknowledge after the reception

of each byte. When the master receiver no longer requires bytes to be transmitter, it must

generate a not-acknowledge. After the not-acknowledge, either a STOP or START

condition must be sent.

A detailed description of the I2C-bus specification is given in Ref. 14 “UM10204”.

PCF85263ATL/A Datasheet(PDF) 64 Page - NXP Semiconductors