PCF85263ATLSLASHA datasheet(42/100 Pages) NXP

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PCF85263A

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Product data sheet

Rev. 4.1 — 27 November 2015

42 of 100

NXP Semiconductors

PCF85263A

Tiny RTC with alarm, battery switch-over, and I2C-bus

8.10 Oscillator register

8.10.1 CLKIV: invert the clock output

[1]

Default value.

The clock selected with the COF[2:0] bits (register Function, address 28h) can be

inverted. This is intended for use in conjunction with the low jitter mode, LOWJ. The low

jitter mode reduces the jitter for the rising edge of the output clock. If the reduced jitter

needs to be on the falling edge, for example when using an open-drain clock output, then

the CLKIV bit can be used to implement this.

8.10.2 OFFM: offset calibration mode

See Section 8.8 “Offset register” on page 34 for a full description of offset calibration.

8.10.3 12_24: 12 hour or 24 hour clock

[1]

Default value.

In RTC mode, time counting can be configured for 24 hour clock or 12 hour clock with the

AMPM flag.

This bit is ignored in stop-watch mode.

8.10.4 LOWJ: low jitter mode

[1]

Default value.

Table 30.

Oscillator - oscillator control register (address 25h) bit description

Bit

Symbol

CLKIV

OFFM

12_24

LOWJ

OSCD[1:0]

CL[1:0]

Section

Section 8.16

Section 8.8

Section 8.10.3

Section 8.10.4

Section 8.10.5

Section 8.10.6

Table 31.

CLKIV bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

7CLKIV

output clock inversion

0[1]

non-inverting; LOWJ mode will affect rising

edge

inverted; LOWJ mode will affect falling edge

Table 32.

12_24 bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

12_24

12 hour or 24 hour mode

0[1]

24 hour mode is selected

12 hour mode is selected

Table 33.

LOWJ bit - oscillator control register (address 25h)

Bit

Symbol

Value

Description

4LOWJ

low jitter CLK output bit

0[1]

normal

reduced CLK output jitter; increase IDD

PCF85263ATL/A Datasheet(PDF) 42 Page - NXP Semiconductors

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