Maximum Duty Cycle =

2

TS - TD - T1

1

TS

LM5035

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SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015

Feature Description (continued)

The LM5035 can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external

clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external

clock frequency is less than the RT resistor programmed frequency, the LM5035 will ignore the synchronizing

pulses. The synchronization pulse width at the RT pin must be a minimum of 15-ns wide. The clock signal must

be coupled into the RT pin through a 100-pF capacitor or a value small enough to ensure the pulse width at RT

is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions low-to-high

(rising edge), the voltage at the RT pin must be driven to exceed 3.2 V from its nominal 2-V DC level. During the

low time of the clock signal, the voltage at the RT pin will be clamped at 2-V DC by an internal regulator. The

output impedance of the RT regulator is approximately 100

Ω. The RT resistor is always required, whether the

oscillator is free running or externally synchronized.

7.3.12 Gate-Driver Outputs (HO and LO)

The LM5035 provides two alternating gate-driver outputs, the floating high-side gate driver HO and the ground

referenced low-side driver LO. Each driver can source 1.25 A and sink 2-A peak. The HO and LO outputs

operate in an alternating manner at one-half of the internal oscillator frequency. The LO driver is powered directly

by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB and HS.

An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high-side gate driver

power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the high-side

MOSFET is turned on, HB rises to a peak voltage equal to VVCC + VHS where VHS is the switch-node voltage.

The HB and VCC capacitors must be placed close to the pins of the LM5035 to minimize voltage transients due

to parasitic inductances because the peak current sourced to the MOSFET gates can exceed 1.25 A. The

recommended value of the HB capacitor is 0.01 µF or greater. A low-ESR or low-ESL capacitor, such as a

surface-mount ceramic, must be used to prevent voltage droop during the HO transitions.

The maximum duty cycle for each output is limited to slightly less than 50%, due to the internally fixed dead time

and any programmed sync rectifier delay. The typical dead time in this condition is 70 ns. The programmed sync

rectifier delay is determined by the DLY pin resistor. If the COMP pin is open circuit, the outputs will operate at

maximum duty cycle. The maximum duty cycle for each output can be calculated with Equation 3:

where

•

TS is the period of one complete cycle for either the HO or LO outputs

•

TD is the internally fixed dead time

•

and T1 is the programmed sync rectifier delay

(3)

For example, if the oscillator frequency is 200 kHz, each output will cycle at 100 kHz (TS = 10 µs). Using the

nominal dead time of 70 ns and no programmed delay, the maximum duty cycle at this frequency is calculated to

be 49.3%. Using a programmed sync rectifier delay of 100 ns, the maximum duty cycle is reduced to 48.3%.

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