LM5035 datasheet(30/40 Pages) TI2

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LM5035

SNVS428H – JANUARY 2006 – REVISED OCTOBER 2015

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8.2.3 Application Curves

Figure 29 shows typical output ripple seen across the output terminals (with standard 10-µF and 1-µF ceramic

capacitors) for an input voltage of 48 V and a load of 30 A. This waveform is typical of most loads and input

voltages.

Figure 30 and Figure 31 show the drain voltage of Q1 with a 5-A load. Figure 30 represents an input voltage of

36 V and Figure 29 represents an input voltage of 72 V.

Figure 32 shows the gate voltages of the synchronous rectifiers. The dead time provided by the 20-k

Ω DLY

resistor is difficult to see at this timescale.

VIN = 48 VDC

Horizontal resolution = 0.5 ms/div

VIN = 48 VDC

Horizontal resolution = 0.5 ms/div

IOUT = 5 A

Trace 1: output voltage V/div = 500 mV

IOUT = 15 A to 22.5 A

Upper trace: VOUT V/div = 50 mV

Lower trace: IOUT = 15 A to 22.5 A to 15 A

Figure 27. Output Voltage During a Typical Start-Up

Figure 28. Transient Response for a Load Change

From 15 A to 22.5 A

VIN = 48 VDC

Trace 1: output ripple voltage V/div = 20 mV

VIN = 36 VDC

Trace 1: Q1 drain voltage V/div = 10 V

IOUT = 30 A

Horizontal resolution = 1 µs/div

IOUT = 5 A

Horizontal resolution = 1 µs/div

Bandwidth limit = 20 MHz

Figure 30. Drain Voltage of Q1 With a 5-A Load

Figure 29. Typical Output Ripple Across the Output

Terminals

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