Not Recommended for New Designs

CDC706

www.ti.com...................................................................................................................................... SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008

Byte 6 Bit [7:5]: VCO Frequency Selection Mode for each PLL (1)

PLLxFVCO

VCO Frequency Range

Default (2)

0

80-200 MHz

1

180-300 MHz

Yes

(1)

This bit selects the normal-speed mode or the high-speed mode for the dedicated VCO in PLL1, PLL2 or PLL3. At power-up, the

high-speed mode is selected, fVCO is 180-300 MHz. In case of higher fVCO, this bit has to be set to [1].

(2)

Unless customer specific setting.

Byte 9 to 12: Outputs Switch Matrix (5x6 Switch A) PLL Selection for P-Divider P0-P5

SWAPx2

SWAPx1

SWAPx0

Any Output Px

Default (1)

0

0

0

PLL bypass (input clock)

0

0

1

PLL1

P2, P3, P4, P5

0

1

0

PLL2 non-SSC

P0

0

1

1

PLL2 w/ SSC(2)

1

0

0

PLL3

P1

1

0

1

Reserved

1

1

0

Reserved

1

1

1

Reserved

(1)

Unless customer specific setting.

(2)

PLL2 has a SSC output and non-SSC output. If SSC bypass is selected (see Byte 25, Bit [6:4]), the SSC circuitry of PLL2 is

powered-down and the SSC output is reset to logic low. The non-SSC output of PLL2 is not affected by this mode and can still be used.

Byte 10, Bit [1:0]: Configuration Settings of Input S0/CLK_SEL

S01

S00

Function

Default (1)

If S0 is low, the PLLs and the clock-input stage are going into power-down mode, outputs are in

Yes

0

0

3-state, all actual register settings will be maintained, SMBus stays active (2)

If S0 is low, the PLL and all dividers (M-Div and P-Div) are bypassed and PLL is in power-down,

0

1

all outputs are active (inv. or non-inv.), actual register settings will be maintained, SMBus stays

active; this mode is useful for production test;

CLK_SEL (input clock selection — overwrites the CLK_SEL setting in Byte 10, Bit [4])(3)

1

0

— CLK_SEL is set low selects CLK_IN_IN0

— CLK_SEL is set high selects CLK_IN_IN1

1

1

Reserved

(1)

Unless customer specific setting.

(2)

Power-down mode overwrites 3-state or low-state of S1 setting in Byte 10, Bit [3:2].

(3)

If the clock input (CLK_IN0/CLK_IN1) is selected as crystal input or differential clock input (Byte 11, Bit [7:6]) then this setting is not

relevant.

Byte 10, Bit [3:2]: Configuration Settings of Input S1

S11

S10

Function

Default (1)

0

0

If S1 is set low, all outputs are switched to a low-state (non-inv.) or high-state (inv.);

Yes

0

1

If S1 is set low, all outputs are switched to a 3-state

1

0

Reserved

1

1

Reserved

(1)

Unless customer specific setting.

Byte 10, Bit [4]: Input Clock Selection (1)

CLKSEL

Input Clock

Default (2)

0

CLK_IN0

Yes

1

CLK_IN1

(1)

This bit is not relevant, if crystal input or differential clock input is selected, Byte 11, Bit [7:6].

(2)

Unless customer specific setting.

Copyright © 2006–2008, Texas Instruments Incorporated

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