−40

−30

−20

−10

0

10

20

30

40

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

−25

−20

−15

−10

−5

0

5

10

15

20

25

1

1001

2001

3001

4001

5001

6001

7001

8001

9001

10001

Cycle

Not Recommended for New Designs

CDC706

SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008...................................................................................................................................... www.ti.com

Figure 26. Snapshot of Cycle-to-Cycle Jitter

Period jitter (tjit(per)) is the deviation in cycle time of a clock signal with respect to the ideal period (1/fo) over a

random sample of cycles. In reference to a PLL, period jitter is the worst-case period deviation from the ideal that

would ever occur on the PLLs outputs. This is also referred to as short-term jitter.

Figure 27. Snapshot of Period Jitter

30

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