EVMBoardConfiguration:

• CLK_IN:Crystal27MHz

Measurement:

• StartCondition: ƒ(M =10,N=30)=81MHz

• Byte2write:N=30(81MHz) N=1

³

10(297MHz)

Result:

• 60 mstoPLL PullIn

• 90 mstoPLL PhaseLock

20 ms/div

81

297

0

60

t[ s]

m

StartCondition:

Acknowledgeof

N-DividerByte

Frequency

Response

Curveof Y0

f

VCO (MHz)

• Y0(PLL1), Y13state

• measuredChannel: Y0

V

t

Typ3.3V

Typ2.1V

Typ1.7V

A

B

C

D

VCC

VPUC_ON

VPUC_OFF

GND

Not Recommended for New Designs

CDC706

www.ti.com...................................................................................................................................... SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008

Figure 33. Snapshot of the PLL Lock-Time

Power Supply Sequencing

The CDC706 includes three power supply pins, VCC, VCCOUT1, and VCCOUT2. There are no power supply

sequencing requirements, as the three power nodes are separated from each other. So, power can be supplied

in any order to the three nodes.

Also, the part has a power-up circuitry which switches the device on if VCC exceeds 2.1 V (typical) and switches

the device off at VCC < 1.7 V (typical). In power-down mode, all outputs and clock inputs are switched off.

Device Behavior During Supply Voltage Drops

The CDC706 has a Power-Up-Circuit, which activates the device function at VPUC_ON (typical 2.1 V). At the same

time, the ROM information is loaded into the register. This mechanism ensures that there is a pre-defined default

after Power-Up and no need to reprogram the CDC706 in the application.

In the event of a supply-voltage-drop, the Power-Up-Circuit assures that there is always a defined setup within

the register. Figure 34 shows possible voltage drops with different amplitudes.

Figure 34. Different Voltage Drops on VCC During Operation

Copyright © 2006–2008, Texas Instruments Incorporated

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Product Folder Link(s): CDC706