1

7

1

1

8

1

1

S

Slave Address

Wr A

Data Byte

A

P

S

Start Condition

Sr

Reapeated Start Condition

Rd Read (Bit Value = 1)

Wr

Write (Bit Value = 0)

A

Acknowledge (ACK = 0 and NACK = 1)

P

Stop Condition

PE

Packet Error

Master-to-Slave Transmission

Slave-to-Master Transmission

Not Recommended for New Designs

CDC706

www.ti.com...................................................................................................................................... SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008

APPLICATION INFORMATION

SMBus Data Interface

To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. It follows

the SMBus specification Version 2.0, which is based upon the principals of operation of I2C. More details of the

SMBus specification can be found at http://www.smbus.org.

Through the SMBus, various device functions, such as individual clock output buffers, can be individually

enabled or disabled. The registers associated with the SMBus data interface initialize to their default setting upon

power-up; therefore, using this interface is optional. The clock device register changes are normally made upon

system initialization, if any are required.

Data Protocol

The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the

controller.

For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte

(most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and

Byte Read operations, the system controller can access individually addressed bytes.

Once a byte has been sent, it is written into the internal register and effective immediately with the rising edge of

the ACK bit. This applies to each transferred byte, independent of whether this is a Byte Write or a Block Write

sequence.

The offset of the indexed byte is encoded in the command code, as described in Table 1.

The Block Write and Block Read protocol is outlined in Figure 9 and Figure 10, while Figure 7 and Figure 8

outlines the corresponding Byte Write and Byte Read protocol.

Slave Receiver Address (7 bits)

A6

A5

A4

A3

A2

A1

A0

R/W

1

1

0

1

0

0

1

0

Table 1. Command Code Definition

Bit

Description

7

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

(6:0)

Byte Offset for Byte Read and Byte Write operation.

Figure 6. Generic Programming Sequence

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