5x6 − Switch A

Input CLK

(PLL Bypass)

PLL 1

PLL 2

non SSC

PLL 2

w/ SSC

PLL 3

6x6 − Switch B

7-Bit Divider

Y0

Y1

Y2

Y3

Y4

Y5

Output Switch Matrix

P0

(1..127)

P2

(1..127)

P3

(1..127)

P4

(1..127)

P5

(1..127)

Programming

Outputs

Internal Clock Sources

PLL/Input_Clk

Selection

P-Divider

Selection

Output Selection:

Active/Low/3-State/

Inverting/Non-Inverting

P-Divider

Setting

P1

(1..127)

Slew Rate/VCCOUT

Div by 3

Inverting

Slew Rate

Low Select

Enable/Disable

Clock

Buffer

Sel

M

U

X

P-div(0)output

P-div(1)output

P-div(2)output

P-div(3)output

P-div(4)output

P-div(5)output

Yx

S1

P-DividerSelect

InversionSelect

Slew-RateControl

LowSelect

Enable/Disable

(Optionalall

outputslow

or3-State)

VCCOUT1/VCCOUT2

Not Recommended for New Designs

CDC706

SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008...................................................................................................................................... www.ti.com

Figure 23. CDC706 Output Switch Matrix

In addition, the outputs can be switched active, low or 3-state and/or 180 degree phase shifted. Also the outputs

slew-rate and the output-voltage is user selectable.

LVCMOS Output Configuration

The output stage of the CDC706 supports all common output setting, such as enable, disable, low-state and

signal inversion (180 degree phase shift). It further features slew-rate control (0.6 ns to 3.3 ns) and variable

output supply voltage (2.3 V to 3.6 V).

Figure 24. Block Diagram of Output Architecture

Figure 25. Example for Output Waveforms

All output settings are programmable via SMBus:

•

enable, disable, low-state via external control pins S0 and S1

→ Byte 10, Bit[3:0]

•

enable or disable-to-low

→ Byte 19 to 24, Bit[3]

•

inverting/non-inverting

→ Byte 19 to 24, Bit[6]

•

slew-rate control

→ Byte 19 to 24, Bit[5:4]

•

output swing

→ external pins VCCOUT1 (Pin 14) and VCCOUT2 (Pin 18)

28

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