−150

−140

−130

−120

−110

−100

−90

−80

−70

−60

−50

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

CDC706Cyrstal27MHzInput

27MHzBufferedOutput

CDC706fOUT 135MHz

f

135MHz

VCO

foffset -[Hz]

CDC706fOUT 135MHz

f

270MHz

VCO

PhaseNoiseComparison

f

135MHz

f

135MHzvs270MHz

OUT

VCO

Not Recommended for New Designs

CDC706

SCAS829B – SEPTEMBER 2006 – REVISED FEBRUARY 2008...................................................................................................................................... www.ti.com

Figure 32. Phase Noise Characteristic - foffset - Hz

PLL Lock-Time

Some applications use frequency switching, i.e. to change frequency in TV application (switching between

channels) or change the PCI-X frequency in computers. The time spent by the PLL in achieving the new

frequency is of main interest. The lock time is the time it takes to jump from one specified frequency to another

specified frequency within a given frequency tolerance (see Figure 33). It should be low, because a long lock

time impacts the data rate of the system.

The PLL-Lock-Time depends on the device configuration and can be changed by the VCO frequency, i.e. by

changing the M/N divider values. Table 7 gives the typical lock times of the CDC706 and Figure 33 shows a

snapshot of a frequency switch.

Table 7. CDC706 PLL Lock-Times

Description

Lock Time

Unit

Frequency change via reprogramming of N/M counter

100

μs

Frequency change via CLK_SEL pin (switching between CLK_IN0 and CLK_IN1)

100

μs

Power-up lock time with system clock

50

μs

Power-up lock time with 27 MHz Crystal at CLK_IN0 and CLK_IN1

300(1)

μs

(1)

Is the result of Crystal lock time (200

μs) and PLL lock time (100 μs).

34

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