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AFE031 Datasheet(PDF) 44 Page - Texas Instruments

Part # AFE031
Description  AFE031 Powerline Communications Analog Front-End
PDF  59 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

AFE031 Datasheet(HTML) 44 Page - Texas Instruments

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AFE031
SBOS531E – AUGUST 2010 – REVISED JUNE 2019
www.ti.com
Product Folder Links: AFE031
Submit Documentation Feedback
Copyright © 2010–2019, Texas Instruments Incorporated
Table 16. RESET Register: Address 0x09
Default: 0x00
Reset Register <7:0>
BIT NAME
LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
--
0
0
--
Reserved
--
1
0
--
Reserved
SOFTRST0,
SOFTRST1,
SOFTRST2
2, 3, 4
0, 0, 0
W
These bits are used to perform a software reset of the ENABLE1,
ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT
registers. Writing '101' to these registers performs a software reset.
T_FLAG
5
0
R/W
This bit is used to indicate the status of a PA thermal overload.
0 = On read, indicates that no thermal overload has occurred since
the last reset.
0 = On write, resets this bit.
1 = On read, indicates that a thermal overload has occurred since
the last reset. Remains latched until reset.
I_FLAG
6
0
R/W
This bit is used to indicate the status of a PA output current
overload.
0 = On read indicates that no current overload has occurred since
the last reset.
0 = On write, resets this bit.
1 = On read indicates that a current overload has occurred since
the last reset. Remains latched until reset.
--
7
0
--
Reserved
Table 17. DieID Register: Address 0x0A
Default: 0x00
DieID Register <7:0>
BIT NAME
LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
DIE ID<0>
0
0
R
The Die ID register is hard-wired.
DIE ID<1>
1
0
R
The Die ID register is hard-wired.
DIE ID<2>
2
0
R
The Die ID register is hard-wired.
DIE ID<3>
3
0
R
The Die ID register is hard-wired.
DIE ID<4>
4
0
R
The Die ID register is hard-wired.
DIE ID<5>
5
0
R
The Die ID register is hard-wired.
DIE ID<6>
6
0
R
The Die ID register is hard-wired.
DIE ID<7>
7
0
R
The Die ID register is hard-wired.
Table 18. Revision Register: Address 0x0B
Default: 0x02
Revision Register <7:0>
BIT NAME
LOCATION
(0 = LSB)
DEFAULT
R/W
FUNCTION
REVISION ID<0>
0
0
R
The revision register is hard-wired.
REVISION ID<1>
1
1
R
The revision register is hard-wired.
REVISION ID<2>
2
0
R
The revision register is hard-wired.
REVISION ID<3>
3
0
R
The revision register is hard-wired.
REVISION ID<4>
4
0
R
The revision register is hard-wired.
REVISION ID<5>
5
0
R
The revision register is hard-wired.
REVISION ID<6>
6
0
R
The revision register is hard-wired.
REVISION ID<7>
7
0
R
The revision register is hard-wired.



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