ADS9217 datasheet(25/68 Pages) TI2

25 / 68 page

Table 7-8. Data Clock (DCLK) Speed

DATA FRAME

WIDTH (Bits)

DATA RATE

(1 = SDR, 2 = DDR)

SMPL_CLK

MULTIPLIER

DCLK (SMPL_CLK =

5MHz)

DCLK (SMPL_CLK =

10MHz)

DCLK (SMPL_CLK =

20MHz)

120MHz

—

60MHz

120MHz

240MHz

100MHz

—(1)

50MHz

—(1)

(1)

A 20-bit data frame width is not supported for the ADS9119 or ADS9118.

7.3.8.1 Data Frame Width

As shown in Figure 7-6, the ADS911x supports 24-bit and 20-bit data frame width options. Configure the

DATA_WIDTH field in address 0x12 to select the data frame width. The default output data frame width is 24

bits. The ADC resolution is 18 bits, represented by 20 bits.

DATA_WIDTH = 0 (20-bit)

18 bit (MSB aligned) ADC conversion result

USER_BITS[1:0]

ADC Output

DATA_WIDTH = 1 (24-bit)

18 bit (MSB aligned) ADC conversion result

USER_BITS[5:0]

ADC Output

Figure 7-6. Data Frame Width Composition

7.3.8.2 ADC Output Data Randomizer

The ADS911x features a data output randomizer. When enabled, the ADC conversion result is bit-wise

exclusive-ORed (XOR). Figure 7-7 illustrates a diagram of such an XOR operation. Either the LSB of the

conversion result (Figure 7-8) or the XOR_PRBS bit (default) is appended to the ADC data output (Figure 7-9).

The LSB of the ADC conversion result and XOR_PRBS have equal probability of being either 1 or 0. As a result

of the XOR operation, the data output from the ADS911x is randomized. The ground bounce created by the

transmission of this randomized result over the data interface is uncorrelated with the analog input voltage. This

uncorrelated transmission helps minimize interference between data transmission and analog performance of

the ADC when the PCB layout does not minimize ground bounce.

MSB

MSB - 1

MSB - 2

LSB + 1

LSB

MSB

MSB - 1

MSB - 2

LSB + 1

LSB

ADC Conversion

Result

Bit-wise

XOR

Randomized

Result

Figure 7-7. Bit-Wise XOR Operation

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ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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ADS9217 Datasheet(PDF) 25 Page - Texas Instruments

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