ADS9217 datasheet(40/68 Pages) TI2

40 / 68 page

8.2.4 Register 13h (offset = 13h) [reset = 0h]

Figure 8-19. Register 13h

RESERVED

R/W-0h

RAMP_INC

TP_MODE

TP_EN

RESERVED

R/W-0h

Figure 8-20. Register 13h Field Descriptions

Bit

Field

Type

Reset

Description

15-8

RESERVED

R/W

Reserved. Do not change from the default reset value.

7-4

RAMP_INC

R/W

Increment value for the ramp pattern output. The output

ramp increments by N+1, where N is the value configured

in this register.

3-2

TP_MODE

R/W

Select digital test pattern for ADC.

0 : Fixed pattern from the TP0 register

1 : Fixed pattern from the TP0 register

2 : Digital ramp output

3 : Alternate fixed pattern output from the TP0 and TP1

registers

TP_EN

R/W

Enable digital test pattern for data corresponding to ADC.

0 : Data output is the ADC conversion result

1 : Data output is the digital test pattern for ADC

RESERVED

R/W

Reserved. Do not change from the default reset value.

8.2.5 Register 14h (offset = 14h) [reset = 0h]

Figure 8-21. Register 14h

TP0[15:0]

R/W-0h

TP0[15:0]

R/W-0h

Figure 8-22. Register 14h Field Descriptions

Bit

Field

Type

Reset

Description

15-0

TP0[15:0]

R/W

Lower 16 bits of test pattern 0

ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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ADS9217 Datasheet(PDF) 40 Page - Texas Instruments

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