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ADS9217 Datasheet(PDF) 46 Page - Texas Instruments |
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ADS9217 Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 68 page ![]() 8.2.16 Register C5h (offset = C5h) [reset = 0h] Figure 8-43. Register C5h 15 14 13 12 11 10 9 8 RESERVED HI_FREQ_EN RESERVED CLK3 RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 RESERVED RD_CLK RESERVED CLK4 RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Figure 8-44. Register C5h Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value. 13 HI_FREQ_EN R/W 0h Fast analog input slew rate enable. 0: Normal slew rate, 1: Fast analog input control enabled. Recommended for input frequencies >2MHz. Also see the HI_FREQ register bit. 12-10 RESERVED R/W 0h Reserved. Do not change from the default reset value. 9 CLK3 R/W 0h Select data rate for the data interface. 0 : Configuration for DATA_LANES = 0 or 2 8 - 7 RESERVED R/W 0h Reserved. Do not change from the default reset value. 6-5 RD_CLK R/W 0h Data output clock control for data averaging. See the Data Averaging section for more details. 4 RESERVED R/W 0h Reserved. Do not change from the default reset value. 3 - 2 CLK4 R/W 0h Clock configuration for ADS9117. See the Data Interface section for details. Not applicable for the ADS9119 and ADS9118. 0 : 24-bit mode 3 : All other modes 1 - 0 RESERVED R/W 0h Reserved. Do not change from the default reset value. ADS9117, ADS9118, ADS9119 SLVSIN3 – MAY 2025 www.ti.com 46 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: ADS9117 ADS9118 ADS9119 |
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