ADS9217 datasheet(10/68 Pages) TI2

10 / 68 page

6.6 Timing Requirements

at AVDD_5V = 4.75V to 5.25V, VDD_1V8 = 1.75V to 1.85V, internal VREF = 4.096V, and maximum throughput (unless

otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C

MIN

MAX

UNIT

CONVERSION CYCLE

fCYCLE

Sampling frequency

ADS9119

MHz

ADS9118

3.9

ADS9117

3.9

tCYCLE

ADC cycle time period

1 / fCYCLE

tPL_SMPLCLK Sample clock low time

0.4

0.6

tCYCLE

tPH_SMPLCLK Sample clock high time

0.4

0.6

tCYCLE

fCLK

Maximum SCLK frequency

MHz

tCLK

Minimum SCLK time period

100

SPI TIMINGS

thi_CSZ

Pulse duration: CS high

220

tPH_CK

SCLK high time

0.48

0.52

tCLK

tPL_CK

SCLK low time

0.48

0.52

tCLK

td_CSCK

Setup time: CS falling to the first SCLK rising edge

tsu_CKDI

Setup time: SDI data valid to the corresponding SCLK rising edge

tht_CKDI

Hold time: SCLK rising edge to corresponding data valid on SDI

td_CKCS

Delay time: last SCLK falling edge to CS rising

ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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ADS9217 Datasheet(PDF) 10 Page - Texas Instruments

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