ADS9217 datasheet(31/68 Pages) TI2

31 / 68 page

24-bits

SCLK

{ addr[23:16] = 0x03, data[15:0] = 0x0002 or

0x0010 }

Not Required for Register Bank 0

{ addr[23:16] = 0x00, data[15:0] = 0x0006 }

{ addr[23:16] = REG_ADDR, data[15:0] = 0 }

{ addr[23:16] = 0x00, data[15:0] = 0x0004 }

SDI

16-bit Register Data

Hi-Z (when SPI_MODE = 1b)

Logic 0 (when SPI_MODE = 0b)

SDO

Frame 1

Frame 2

Frame 3

Frame 4

Figure 7-14. Register Read

7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration

Figure 7-15 shows a typical connection diagram showing multiple devices in a daisy-chain topology.

24-bit

ADS91XX

ADC1

SDI

SDO

24-bit

ADS91XX

ADC2

SDI

SDO

24-bit

ADS91XX

ADC3

SDI

SDO

24-bit

ADS91XX

ADC4

SDI

SDO

PICO

POCI

SCLK

HOST

SCLK

Figure 7-15. Daisy-Chain Connections for SPI Configuration

The CS and SCLK inputs of all ADCs are connected together and controlled by a single CS and SCLK pin of

the controller, respectively. The SDI input pin of the first ADC in the chain (ADC1) is connected to the peripheral

IN controller OUT (PICO) pin of the controller. The SDO output pin of ADC1 is connected to the SDI input pin of

ADC2, and so on. The SDO output pin of the last ADC in the chain (ADC4) is connected to the peripheral OUT

controller IN (POCI) pin of the controller. The data on the PICO pin passes through ADC1 with a 24-SCLK delay,

as long as CS is active.

Enable daisy-chain mode after power-up or after the device is reset. Set the daisy-chain length in the

DAISY_CHAIN_LENGTH register to enable daisy-chain mode. The daisy-chain length is the number of ADCs in

the chain, excluding ADC1. In Figure 7-15, the DAISY_CHAIN_LENGTH is 3.

7.5.3.1 Register Write With Daisy-Chain

Writing to registers in daisy-chain configuration requires N × 24 SCLKs in one SPI frame. Register writes in a

daisy-chain configuration containing four ADCs, as illustrated in Figure 7-15, requires 96 SCLKs.

Daisy-chain mode is enabled on power-up or after device reset. Configure the DAISY_CHAIN_LENGTH field to

enable daisy-chain mode. Repeat the waveform in Figure 7-16 N times, where N is the number of ADCs in the

daisy chain. Figure 7-17 provides the SPI waveform, containing N SPI frames, for enabling daisy-chain mode for

N ADCs.

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