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ADS9217 Datasheet(PDF) 44 Page - Texas Instruments |
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ADS9217 Datasheet(HTML) 44 Page - Texas Instruments |
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44 / 68 page ![]() 8.2.13 Register C0h (offset = C0h) [reset = 0h] Figure 8-37. Register C0h 15 14 13 12 11 10 9 8 RESERVED CLK1 OSR_INIT1 OSR_CLK R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h 7 6 5 4 3 2 1 0 OSR_CLK RESERVED PD_CH R/W-0h R/W-0h R/W-0h Figure 8-38. Register C0h Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h Reserved. Do not change from the default reset value. 12 CLK1 R/W 0h Selects the clock configuration based on output data lanes. 0 : Configuration for DATA_LANES = 0 or 2 1 : Not recommended 11-10 OSR_INIT1 R/W 0h Initialization for data averaging. 0 : Configuration for disabling data averaging 1 : Configuration for enabling data averaging 9-7 OSR_CLK R/W 0h Data output clock configuration for data averaging. See Table 7-3 for more details. 6-2 RESERVED R/W 0h Reserved. Do not change from the default reset value. 1-0 PD_CH R/W 0h Power-down control for the analog input channels. 0 : Normal operation 1 : ADC powered down 2 : No effect 3 : ADC powered down ADS9117, ADS9118, ADS9119 SLVSIN3 – MAY 2025 www.ti.com 44 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: ADS9117 ADS9118 ADS9119 |
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