ADS9217 datasheet(26/68 Pages) TI2

26 / 68 page

DATA_WIDTH = 0 (20-bit)

18 bit (MSB aligned) ADC A conversion result

USER_BITS_ADC_A[1:0]

18 bit (MSB aligned) ADC B conversion result

USER_BITS_ADC_B[1:0]

ADC A Output

ADC B Output

DATA_WIDTH = 1 (24-bit)

18 bit (MSB aligned) ADC A conversion result

USER_BITS_ADC_A[5:0]

18 bit (MSB aligned) ADC B conversion result

USER_BITS_ADC_B[5:0]

ADC A Output

ADC B Output

Figure 7-8. Data Frame Width Composition With LSB XOR Enabled

DATA_WIDTH = 0 (20-bit)

DATA_WIDTH = 1 (24-bit)

18 bit (MSB aligned) ADC conversion result

USER_BITS[4:0]

ADC Output

18 bit (MSB aligned) ADC conversion result

USER_BITS[0]

ADC Output

MSB (bit 19)

bit 2

LSB (bit 0)

bit 1

MSB (bit 23)

bit 6

LSB (bit 0)

bit 5

Figure 7-9. Data Frame Width Composition With PRBS XOR Enabled

7.3.8.3 Synchronizing Multiple ADCs

Drive the SMPL_CLK pins of the respective ADS911x devices with a common sampling clock. Match the timing

delay on the clock path external to the ADCs by using identical PCB trace lengths for SMPL_CLK for the

respective ADCs.

Use the SMPL_SYNC pin to synchronize multiple ADCs when using the internal decimation filter. The

SMPL_SYNC pin is latched by the falling edge of the sampling clock. A pulse on SMPL_SYNC resets the

internal decimation filter.

ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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Product Folder Links: ADS9117 ADS9118 ADS9119

ADS9217 Datasheet(PDF) 26 Page - Texas Instruments

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