ADS9217 datasheet(29/68 Pages) TI2

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7.4 Device Functional Modes

7.4.1 Reset

Power down the ADS911x with a logic 0 on the RESET pin or write 1b to the RESET field (address 0x00,

sequence of register write operations; see the Initialization Sequence section.

7.4.2 Power-Down Options

Power down the ADS911x with a logic 0 on the PWDN pin or write 11b to the PD_CH field (address 0xC0,

a sequence of register write operations; see the Initialization Sequence section.

7.4.3 Normal Operation

In normal operating mode, the ADS911x powers up and digitizes the analog inputs at the sampling clock falling

edge. The ADC outputs the data clock, frame clock, and MSB-aligned, 18-bit conversion result.

7.4.4 Initialization Sequence

The ADS911x register map is initialized with default values on power-up. Table 7-11 lists the steps to enable

gain error calibration (recommended) and change the output data interface. For the ADS9119 only, follow the

initialization steps in Table 7-12.

Table 7-11. User-Defined Configuration for the ADS9119, ADS9118, and ADS9117

STEP NUMBER

COMMENT

BANK

ADDRESS

VALUE[15:0]

0x0D

User defined

Enable gain error

calibration and select ADC

output data format

0x33

0x2040

Enable gain error

calibration

0x04

0x0000 for data frame

width = 24 bits

0x000B for data frame

width = 20

Table 7-12. Initialization Configuration for the ADS9119 Only

STEP NUMBER

BANK

ADDRESS

VALUE[15:0]

0x0D [9:8]

0x3

0x34 [1]

0x1

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ADS9117, ADS9118, ADS9119

SLVSIN3 – MAY 2025

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