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BQ24192 Datasheet(PDF) 9 Page - Texas Instruments |
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BQ24192 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 53 page  bq24190, bq24192, bq24192I www.ti.com SLUSAW5B – JANUARY 2012 – REVISED DECEMBER 2014 Electrical Characteristics (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBTST-VSW when LSFET refresh pulse is 3.6 requested, VBUS = 5 V VBTST_REFRESH Bootstrap refresh comparator threshold V VBTST-VSW when LSFET refresh pulse is 4.5 requested, VBUS > 6 V BOOST MODE OPERATION VOTG_REG OTG output voltage I(VBUS) = 0 5.00 V VOTG_REG_ACC OTG output voltage accuracy I(VBUS) = 0 –2% 2% REG01[0] = 0 0.5 A IOTG OTG mode output current REG01[0] = 1 1.3 A VOTG_OVP OTG over-voltage threshold 5.3 5.5 V IOTG_ILIM LSFET cycle-by-cycle current limit 3.2 4.6 A IOTG_HSZCP HSFET under current falling threshold 100 mA REG01[0] = 1 1.4 1.8 2.7 IRBFET_OCP RBFET over-current threshold A REG01[0] = 0 0.6 1.1 1.8 REGN LDO VVBUS = 10 V, IREGN = 40 mA 5.6 6 6.4 V VREGN REGN LDO output voltage VVBUS = 5 V, IREGN = 20 mA 4.75 4.8 V IREGN REGN LDO current limit VVBUS = 10 V, VREGN = 3.8 V 50 mA LOGIC I/O PIN CHARACTERISTICS (OTG, CE, PSEL, STAT, PG) VILO Input low threshold 0.4 V VIH Input high threshold 1.3 V VOUT_LO Output low saturation voltage Sink current = 5 mA 0.4 V IBIAS High level leakage current Pull up rail 1.8 V 1 µA I2C INTERFACE (SDA, SCL, INT) VIH Input high threshold level VPULL-UP = 1.8 V, SDA and SCL 1.3 V VIL Input low threshold level VPULL-UP = 1.8 V, SDA and SCL 0.4 V VOL Output low threshold level Sink current = 5 mA 0.4 V IBIAS High-level leakage current VPULL-UP = 1.8 V, SDA and SCL 1 µA fSCL SCL clock frequency 400 kHz DIGITAL CLOCK AND WATCHDOG TIMER fHIZ Digital crude clock REGN LDO disabled 15 35 50 kHz fDIG Digital clock REGN LDO enabled 1300 1500 1700 kHz tWDT REG05[5:4] = 11 REGN LDO enabled 136 160 sec 8.6 Typical Characteristics Table 1. Table of Figures FIGURE NO. System Light Load Efficiency vs System Load Current Figure 1 SYS Voltage Regulation vs System Load Figure 2 Charging Efficiency vs Charging Current Figure 3 Boost Mode Efficiency vs VBUS Load Current Figure 4 Boost Mode VBUS Voltage Regulation vs VBUS Load Current Figure 5 SYS Voltage vs Temperature Figure 6 BAT Voltage vs Temperature Figure 7 Input Current Limit vs Temperature Figure 8 Charge Current vs Temperature Figure 9 Copyright © 2012–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: bq24190 bq24192 bq24192I |
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