CDCM6208 datasheet(26/94 Pages) TI2

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Control

Output

PLL

Input

8-b,10-b

4-b

Host

Interface

Status/

Monitoring

Power

Conditioning

CDCM6208

Differential/

LVCMOS

Differential

LVCMOS/

XTAL

LVPECL/

CML/

LVDS

LVDS/

LVCMOS/

HCSL

Fractional Div

14-b

Integer Div

LVDS/

LVCMOS/

HCSL

VCO:

V1: (2.39-2.55) GHz

and V2: (2.94-3.13) GHz

PRI_REF

SEC_REF

Integer Div

PreScaler PS_A

÷4, ÷5, ÷6

ELF

REF_SEL

Fractional Div

20-b

8-b

Fractional Div

20-b

Fractional Div

20-b

PreScaler PS_B

÷4, ÷5, ÷6

CDCM6208

SCAS931G – MAY 2012 – REVISED JANUARY 2018

www.ti.com

Product Folder Links: CDCM6208

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8 Detailed Description

8.1 Overview

In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp

on output using integer dividers and is between 50 to 220 ps-pp on outputs using fractional dividers depending

on the prescaler output frequency.

In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output

using integer dividers and is less than 70 to 240 ps-pp on outputs using fractional dividers. The CDCM6208 is

packaged in a small 48-pin, 7-mm × 7-mm VQFN package.

8.2 Functional Block Diagram

8.3 Feature Description

Supply Voltage: The CDCM6208 supply is internally regulated. Therefore, each core and I/O supply can be

mixed and matched in any order according to the application needs. The device jitter performance is independent

of supply voltage.

Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and

VCO that operates from 2.39 GHz to 2.55 GHz (CDCM6208V1) and 2.94 GHz to 3.13 GHz (CDCM6208V2).

Reference inputs: The primary and secondary reference inputs support differential and single ended signals

from 8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. There is

a 4-bit reference divider available on the primary reference input. The input mux between the two references

supports simply switching or can be configured as Smart MUX and supports glitchless input switching.

Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the

output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent

prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then

be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an

output MUX. A total of 2 output MUXes are available.

Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz.

The charge pump gain is programmable and the loop filter consists of internal + partially external passive

components and supports bandwidths from a few Hz up to 400 kHz.

CDCM6208 Datasheet(PDF) 26 Page - Texas Instruments

CDCM6208 Datasheet(HTML) 26 Page - Texas Instruments

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