CDCM6208 datasheet(66/94 Pages) TI2

Part #	CDCM6208

Description	CDCM6208 2:8 Clock Generator, Jitter Cleaner With Fractional Dividers

PDF	94 Pages

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Manufacturer	TI2 [Texas Instruments]

Direct Link	https://www.ti.com

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66 / 94 page

De-Serializer

Serializer

TX REF

CLOCK

TX PLL

serial data with

embedded clock

CDR

RX REF

CLOCK

fhigh=BWTX PLL

RX PLL

flow=BWRX PLL

fhigh

flow

HTransfer(f) = HTXPLL * ( 1 - HRXPLL)

flow=1.875MHz for 10GbE

fhigh=20MHz for 10GbE

CDCM6208

SCAS931G – MAY 2012 – REVISED JANUARY 2018

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Typical Applications (continued)

Figure 50. Serial Link Jitter Budget Explanation

Example: SERDES link with KeyStone™ I DSP

The SERDES TX PLL of the TI KeyStone™ I DSP family (see Hardware Design Guide for KeyStone Devices

(SPRABI2)) for the SRIO interface has a 13-MHz PLL bandwidth (Low Pass Characteristic, see Figure 50). The

CDCM6208V2, pin-mode 27, was characterized in this example over Process, Voltage and Temperature (PVT)

with a low-pass filter of 13 MHz to simulate the TX PLL. The attenuation is higher or equal to 20 dB/dec;

therefore, the characterization used 20 dB/dec as worst case.

CDCM6208 Datasheet(PDF) 66 Page - Texas Instruments