CDCM6208 datasheet(13/94 Pages) TI2

13 / 94 page

CDCM6208

www.ti.com

SCAS931G – MAY 2012 – REVISED JANUARY 2018

Product Folder Links: CDCM6208

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6.15

LVPECL (High-Swing CML) Output Characteristics

VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625

V, 3.135 V to 3.465 V, TA = –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT-I

Output frequency

Integer Output Divider

CDCM6208V1

1.55

800

MHz

CDCM6208V2

1.91

800

VCM-DC

Output DC-coupled common-

mode voltage

DC coupled with 50-Ω external termination to

VDD_Yx_Yy

VDD_Yx_Yy – 0.4

|VOD|

Differential output voltage

100-Ω diff load AC coupling (see Figure 12),

fOUT ≤ 250 MHz

1.71 V

≤ VDD_Yx_Yy ≤ 1.89 V

0.45

0.75

1.12

2.375 V

≤ VDD_Yx_Yy ≤ 3.465 V

0.6

0.8

1.12

100-Ω diff load AC coupling (see Figure 12), fOUT ≥

250

1.71 V

≤ VDD_Yx_Yy ≤ 1.89 V

0.73

2.375 V

≤ VDD_Yx_Yy ≤ 3.465 V

0.55

0.75

1.12

VOUT

Differential output peak-to-

peak voltage

2 ×

|V OD|

tR/tF

Output rise/fall time

±200 mV around crossing point

109

217

20% to 80% VOD

211

tslew

Output rise/fall slew rate

3.7

5.1

7.3

V/ns

PN-floor

Phase noise floor

VDD_Yx_Yy = 3.3 V (see Figure 54)

–161.4

–155.8

dBc/Hz

ODC

Output duty cycle

Not in bypass mode

47.5%

52.5%

ROUT

Output impedance

Measured from pin to VDD_Yx_Yy

6.16

CML Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375V to 2.625 V, 3.135 V to 3.465

V, TA = –40°C to 85°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fOUT-I

Output frequency

Integer output divider

1.55

800

MHz

1.91

800

VCM-AC

Output AC-coupled common-

mode voltage

AC-coupled with 50-Ω receiver termination

VDD_Yx_Yy –

0.46

VCM-DC

Output DC-coupled common-

mode voltage

DC-coupled with 50-Ω on-chip termination to

VDD_Yx_Yy

VDD_Yx_Yy –

0.2

|VOD|

Differential output voltage

100-Ω diff load AC coupling (see Figure 12)

0.3

0.45

0.58

VOUT

Differential output peak-to-

peak voltage

2 × |V

OD|

tR/tF

Output rise/fall time

20% to 80%

VDDYx = 1.8 V

100

151

300

VDDYx = 2.5 V/3.3 V

100

143

200

PN-floor

Phase noise floor at > 5-Hz

offset

fOUT = 122.88 MHz

VDD_Yx_Yy = 1.8 V

–161.2-

–155.8

dBc/Hz

VDD_Yx_Yy = 3.3 V

161.2

–153.8

dBc/Hz

ODC

Output duty cycle

Not in bypass mode

47.5%

52.5%

ROUT

Output impedance

Measured from pin to VDD_Yx_Yy

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