CDCM6208 datasheet(49/94 Pages) TI2

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SDA

Data in

Data out

CDCM6208

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SCAS931G – MAY 2012 – REVISED JANUARY 2018

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8.4.5.2.4

2C Serial Interface

With SI_MODE1=0 and SI_MODE0=1 the CDCM6208 enters I 2C mode. The I2C port on the CDCM6208 works

as a slave device and supports both the 100 kHz standard mode and 400 kHz fast mode operations. Fast mode

imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses of less

than 50 ns duration. The inputs of the device also incorporates a Schmitt trigger at the SDA and SCL inputs to

provide receiver input hysteresis for increased noise robustness.

NOTE

Communication through I2C is not possible while RESETN is held low.

In an I2C bus system, the CDCM6208 acts as a slave device and is connected to the serial bus (data bus SDA

and clock bus SCL). The SDA port is bidirectional and uses an open drain driver to permit multiple devices to be

connected to the same serial bus. The CDCM6208 allows up to four unique CDCM6208 slave devices to occupy

the I2C bus in addition to any other I2C slave device with a different I2C address. These slave devices are

accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave

address responds to subsequent I2C commands. The device slave address is 10101xx (the two LSBs are

determined by the AD1 and AD0 pins). The five MSBs are hard-wired, while the two LSBs are set through pins

on device power up.

Figure 44. I2C Serial Interface

During the data transfer through the I2C port interface, one clock pulse is generated for each data bit transferred.

The data on the SDA line must be stable during the high period of the clock. The high or low state of the data

line can change only when the clock signal on the SCL line is low. The start data transfer condition is

characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is

characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are

always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed

by an acknowledge bit and bytes are sent MSB first.

The acknowledge bit (A) or non-acknowledge bit (A) is the 9thbit attached to any 8-bit data byte and is always

generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A

= 1). A = 0 is done by pulling the SDA line low during the 9thclock pulse and A = 1 is done by leaving the SDA

line high during the 9thclock pulse.

CDCM6208 Datasheet(PDF) 49 Page - Texas Instruments