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INA821 Datasheet(PDF) 33 Page - Texas Instruments |
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INA821 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 43 page ![]() Use ground pours for shielding the input signal pairs 1 RG 8 RG 2 ±IN 7 +VS 3 +IN 6 OUT 4 -VS 5 REF R1 R2 C1 C2 GND GND +V ±IN +IN OUT Input traces routed adjacent to each other -V R3 Ground plane removed at gain resistor to minimize parasitic capacitance Low-impedance connection for reference terminal Place bypass capacitors as close to IC as possible R3 +IN -IN +V OUT -V Copyright © 2017, Texas Instruments Incorporated R1 R2 C1 C2 RG INA818 RG 33 INA818 www.ti.com SBOS894A – APRIL 2019 – REVISED JUNE 2019 Product Folder Links: INA818 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 11.2 Layout Example Figure 75. Example Schematic and Associated PCB Layout |
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