L99DZ320 datasheet(131/146 Pages) STMICROELECTRONICS

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Table 121. Status register 8 description

Bit

Name

Description

EI2_WAKE

External interrupt 2 wake-up

‘1’ means wake-up from external interrupt 2

Bit is latched until a “Read & Clear” command

22:21

RESERVED

EI1_WAKE

External interrupt 1 wake-up

‘1’ means wake-up from external interrupt

Bit is latched until a “Read & Clear” command

WAKE_CAN

Wake-up from CAN

‘1’ means wake-up from CAN

Bit is latched until a “Read & Clear” command

WAKE_LIN

Wake-up from LIN

‘1’ means wake-up from LIN

Bit is latched until a “Read & Clear” command

WAKE_TIMER

Wake-up from timer

‘1’ means wake-up from timer

Bit is latched until a “Read & Clear” command

DEBUG_ACTIVE

Debug mode active

‘1’ means debug mode

Bit is latched until a “Read & Clear” command

V1UV

Voltage regulator V1 undervoltage

‘1’ indicates undervoltage condition at voltage regulator V1 (V1 < VRTx)

Bit is latched until a “Read & Clear” command

V1_RESTART_2

Voltage regulator V1 restart

Indicates the number of TSD2 events that caused a restart of voltage regulator V1

Bits cannot be cleared; the counter is cleared automatically if no additional TSD2 event occurs

within 1 minute

V1_RESTART_1

V1_RESTART_0

WDFAIL_CNT_3

Watchdog failure counter

Indicates number of subsequent watchdog failures

Bits cannot be cleared; is cleared with a valid watchdog trigger

WDFAIL_CNT_2

WDFAIL_CNT_1

WDFAIL_CNT_0

DEVICE_STATE_1

V2 short-circuit detection

Actual state

00 active mode after power-on or after “Read & Clear” command

01 active mode after wake-up from V1_Standby mode (before “Read & Clear” command)

10 active mode after wake-up from VBAT_Standby mode (before “Read & Clear” command)

11 not used

Bit is latched until a “Read & Clear” command; after a “Read & Clear access”, the device state is

updated

DEVICE_STATE_0

TSD2

Thermal shutdown 2

‘1’ indicates thermal shutdown 2 was reached

Bit is latched until a “Read & Clear” command

TSD1

Thermal shutdown 1

‘1’ indicates thermal shutdown 1 was reached

Bit is latched until a “Read & Clear” command

L99DZ320

SPI Registers

DS14235 - Rev 5

page 131/146

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