L99DZ320 datasheet(129/146 Pages) STMICROELECTRONICS

129 / 146 page

Bit

Name

Description

LIN bus signal is dominant for t > Tdom(bus)

Bit is latched until a “Read & Clear” command

LIN_TXD_DOM

LIN TXD signal dominant timeout

TXDL pin is dominant for t > tdom(TXDL)

The LIN transmitter is disabled until the bit is cleared. Bit is latched until a “Read & Clear” command

LIN_PERM_REC

LIN bus signal permanent recessive

LIN bus signal does not follow TXDL within tLIN

The LIN transmitter is disabled until the bit is cleared. Bit is latched until a “Read & Clear” command

CAN_RXD_REC

CAN RXD signal permanent recessive

RXDC has not followed TXDC for 4 times

The CAN transmitter is disabled until the bit is cleared. Bit is latched until a “Read & Clear” command

CAN_PERM_REC

CAN bus signal permanent recessive

CAN bus signal did not follow TXDC for 4 times

The CAN transmitter is disabled until the bit is cleared. Bit is latched until a “Read & Clear” command

CAN_PERM_DOM

CAN bus signal permanent dominant

CAN bus signal is dominant for t > tCAN

Bit is latched until a “Read & Clear” command

CAN_TXD_DOM

CAN TXD signal permanent dominant

TXDC pin is dominant for t > tdom(TXDC)

The CAN transmitter is disabled until the bit is cleared. Bit is latched until a “Read & Clear” command

CANTO

CAN communication timeout

Bit is set if there is no communication on the bus for t > tSilence; CANTO indicates that there was a transition

from BIAS ON to BIAS OFF

Bit is latched until a “Read & Clear” command

DSMON_HS2

Drain-source monitoring HS2

‘1’ indicates a short-circuit or open-load condition was detected

Bit is latched until a “Read & Clear” command

DSMON_HS1

Drain-source monitoring HS1

‘1’ indicates a short-circuit or open-load condition was detected

Bit is latched until a “Read & Clear” command

DSMON_LS2

Drain-source monitoring LS2

‘1’ indicates a short-circuit or open-load condition was detected

Bit is latched until a “Read & Clear” command

DSMON_LS1

Drain-source monitoring LS1

‘1’ indicates a short-circuit or open-load condition was detected

Bit is latched until a “Read & Clear” command

SPI_INV_CMD

Invalid SPI command

‘1’ indicates one of the following conditions was detected:

•

Access to undefined address

•

Write operation to Status Register

•

DI stuck at '0' or '1'

•

CSN timeout

•

Parity failure

•

Invalid or undefined setting

The SPI frame is ignored. Bit is latched until a “Read & Clear” command

L99DZ320

SPI Registers

DS14235 - Rev 5

page 129/146

L99DZ320 Datasheet(PDF) 129 Page - STMicroelectronics

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