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L99DZ320 Datasheet(PDF) 125 Page - STMicroelectronics |
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L99DZ320 Datasheet(HTML) 125 Page - STMicroelectronics |
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125 / 146 page  6.5.4 Status register 4 (0x04) Table 112. Status register 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name Access R&C R R&C R Table 113. Status register 4 description Bit Name Description 23 WD_TIMER_STATE_1 Watchdog timer status Status 00 0 - 33% 01 33 - 66% 11 66 - 100% 10 invalid configuration 22 WD_TIMER_STATE_0 21 EI2_STATE State of EI2 input 0 input level is low 1 input level is high The bit shows the momentary status of EI2 and cannot be cleared (“live bit”) Note: the status is only valid if it has been configured as wake-up input in CR1 (0x26). Otherwise this bit is read as ‘0’ 20 RESERVED - 18 EI1_STATE State of EI1 input 0 input level is low 1 input level is high The bit shows the momentary status of EI1 and cannot be cleared (“live bit”) 17:0 RESERVED - L99DZ320 SPI Registers DS14235 - Rev 5 page 125/146 |
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