L99DZ320 datasheet(121/146 Pages) STMICROELECTRONICS

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Bit

Name

Description

10 External Interrupt 1 monitored in cyclic mode with Timer 1 (filter time: tWU_cyc; blanking time 80% of

timer ON time)(1)

11 Invalid setting; command is ignored and SPI INV CMD is set

HEN

Enable H-bridge

0: H-bridge disabled (default)

1: H-bridge enabled

Refer to Section 2.4.13: H-bridge driver for details.

CAN_REC_ONLY

CAN receive only mode

0: CAN receive Only mode disabled (default)

1: CAN receive Only mode enabled (CAN Trx must be activated, see CAN_ACT bit)

CAN_ACT

CAN transceiver activation

0: CAN Trx low-power mode (default)

1: CAN Trx normal mode

LIN_WU_EN (2)

Enable wake-up by LIN

0: disabled

1: enabled (default)

Note: the wake-up behavior is configurable in the CR1 (0x26).

CAN_WU_EN (2)

Enable wake-up by CAN

0: disabled

1: enabled (default)

Note: wake-up occurs at a wake–up event according to ISO 11898-2.

TIME_NINT_WAKE_SEL

Select timer for periodic interrupt in standby modes

0: Timer 2 (default)

1: Timer 1

TIMER_NINT_ EN

Enable timer interrupt in standby modes

0: Timer Interrupt disabled (default)

1: Timer Interrupt enabled

V1_Standby mode: device wakes up and interrupt signal is generated at RXDL/NINT when

programmable time-out has elapsed.

VBAT_Standby mode: device wakes up after timer expiration and generates Nreset.

TRIG

Watchdog Trigger bit

1. Lower is the timer duration and major is the contribution of output td ON.

2. Either LIN or CAN must be enabled as wake-up source. Setting both bits 3 and 4 to ‘0’ is an invalid setting. All wake-up sources are

configured according to default setting; SPI Error Bit (SPIE) in Global Status Register is set.

L99DZ320

SPI Registers

DS14235 - Rev 5

page 121/146

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