VDD

INA

OUTA

INB

OUTB

VIT+(INA)

V

HYS

V

HYS

t

pd(LH)

t

pd(LH)

t

pd(LH)

t

pd(HL)

t

pd(HL)

VIT±(INA)

VIT+(INB)

VIT±(INB)

t

d(start)

V(POR)

6

TLV6710

SNVSAV4B – JANUARY 2018 – REVISED OCTOBER 2018

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(1)

High-to-low and low-to-high refers to the transition at the input pins (INA and INB).

(2)

During power on, VDD must exceed 1.8 V for at least 150 µs (typ) before the output state reflects the input condition.

7.6 Timing Requirements

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

.tpd(HL)

High-to-low propagation delay(1)

VDD = 24 V, ±10-mV input overdrive,

RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV

9.9

µs

tpd(LH)

Low-to-high propagation delay(1)

VDD = 24 V, ±10-mV input overdrive,

RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV

28.1

µs

td(start)

(2)

Startup delay

VDD = 5 V

155

µs

tr

Output rise time

VDD = 12 V, 10-mV input overdrive,

RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD

2.7

µs

tf

Output fall time

VDD = 12 V, 10-mV input overdrive,

RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD

0.12

µs

Figure 1. Timing Diagram