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TLV6710

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SNVSAV4B – JANUARY 2018 – REVISED OCTOBER 2018

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8.3 Feature Description

8.3.1 Inputs (INA, INB)

The TLV6710 combines two comparators with a precision reference voltage. Each comparator has one external

input; the other input is connected to the internal reference. The rising threshold on INB and the falling threshold

on INA are designed and trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the

device accuracy when used as a window comparator. Both comparators also have built-in hysteresis that proves

immunity to noise and ensures stable operation.

The comparator inputs swings from ground to 1.7 V (7.0 V absolute maximum), regardless of the device supply

voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF

bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage

changes on the monitored signal.

For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA voltage drops

below VIT–(INA). When the voltage exceeds VIT+(INA), OUTA goes to a high-impedance state; see Figure 1.

For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB exceeds

VIT+(INB). When the voltage drops below VIT–(INB) OUTB goes to a high-impedance state; see Figure 1. Together,

these two comparators form a window-detection function as described in the Window Comparator Considerations

section.

8.3.2 Outputs (OUTA, OUTB)

In a typical TLV6710 application, the outputs are connected to a GPIO input of the processor (such as a digital

signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-

specific integrated circuit [ASIC]).

The TLV6710 provides two open-drain outputs (OUTA and OUTB); use pullup resistors to hold these lines high

when the output goes to a high-impedance state. Connect pullup resistors to the proper voltage rails to enable

the outputs to be connected to other devices at correct interface voltage levels. The TLV6710 outputs can be

pulled up to 25 V, independent of the device supply voltage. To ensure proper voltage levels, give some

consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, output

capacitive loading, and output leakage current (ID(leak)). These values are specified in the Electrical

Characteristics table. Use wired-OR logic to merge OUTA and OUTB into one logic signal.

Table 2 and the Inputs (INA, INB) section describe how the outputs are asserted or high impedance. See

Figure 1 for a timing diagram that describes the relationship between threshold voltages and the respective

output.

8.4 Device Functional Modes

8.4.1 Normal Operation (VDD > UVLO)

When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUTA and OUTB signals correspond to

the voltage on INA and INB as listed in Table 2.

8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)

When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,

V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on

INA and INB.

8.4.3 Power On Reset (VDD < V(POR))

When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND

(V(POR)), both outputs are in a high-impedance state.