R =

2

- R3

V

IT (INA)

-

R

V

TOTAL

MON(UV)

R =

2

- R3

V

IT+(INA)

R

V

TOTAL

MON(UV_HYS)

R =

3

V

IT+(INB)

R

V

TOTAL

MON(OV)

13

TLV6710

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SNVSAV4B – JANUARY 2018 – REVISED OCTOBER 2018

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Application Information (continued)

The TLV6710 flags the overvoltage or undervoltage condition with the greatest accuracy. The highest accuracy

threshold voltages are VIT–(INA) and VIT+(INB), and correspond with the falling undervoltage flag, and the rising

overvoltage flag, respectively. These thresholds represent the accuracy when the monitored voltage is within the

valid window (both OUTA and OUTB are in a high-impedance state), and correspond to the VMON(UV) and

VMON(OV) trigger voltages, respectively. If the monitored voltage is outside of the valid window (VMON is less than

the undervoltage limit, VMON(UV), or greater than overvoltage limit, VMON(OV)), then the input threshold voltages to

re-enter the valid window are VIT+(INA) or VIT–(INB), and correspond with the VMON(UV_HYS) and VMON(OV_HYS)

monitored voltages, respectively.

The resistor divider values and target threshold voltage can be calculated by using Equation 1 through

Equation 4:

RTOTAL = R1 + R2 + R3

(1)

Choose an RTOTAL value so that the current through the divider is approximately 100 times higher than the input

current at the INA and INB pins. Resistors with high values minimize current consumption; however, the input

bias current degrades accuracy if the current through the resistors is too low. See application report Optimizing

Resistor Dividers at a Comparator Input (SLVA450), for details on sizing input resistors.

R3 is determined by Equation 2:

where

•

VMON(OV) is the target voltage at which an overvoltage condition is detected.

(2)

R2 is determined by either Equation 3 or Equation 4:

where

•

VMON(UV_HYS) is the target voltage at which an undervoltage condition is removed as VMON rises.

(3)

where

•

VMON(UV) is the target voltage at which an undervoltage condition is detected.

(4)

9.1.2 Input and Output Configurations

Figure 21 to Figure 23 show examples of the various input and output configurations.