MPQ7920 datasheet(24/44 Pages) MPS

24 / 44 page

MPQ7920

– 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100

MPQ7920 Rev. 1.0

www.MonolithicPower.com

7/13/2020

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

I2C INTERFACE

I2C Serial Interface Description

The I2C is a two-wire, bidirectional serial

interface consisting of a data line (SDA) and a

clock line (SCL). The lines are externally pulled

to a bus voltage when they are idle. A master

device is connected to the line; it generates the

SCL signal and device address, and arranges

the communication sequence.

The MPQ7920 interface is an I2C slave that can

support fast mode (400kHz) and high-speed

mode (3.4Mhz). The I2C interface adds flexibility

to the power supply solution. Among other

parameters, the output voltage and transition

slew rate can be instantaneously controlled by

the I2C interface. If the master sends the address

as an 8-bit value, the 7-bit address should be

followed by 0 or 1 to indicate a read or write (R/W)

operation, respectively.

Start and Stop Conditions

The start and stop conditions are signaled by the

master device, and signify the beginning and the

end of the I2C transfer. The start (S) condition is

defined as the SDA signal transitioning from high

to low while the SCL is high. The stop (P)

condition

defined

the

SDA

signal

transitioning from low to high while the SCL is

high (see Figure 12).

The master then generates the SCL clocks, and

transmits the device address and the R/W

direction bit on the SDA line.

SDA

SCL

Start Condition

Stop Condition

Figure 12: Start and Stop Conditions

Transfer Data

Data is transferred in 8-bit bytes by the SDA line.

Each byte of data should be followed by an

acknowledge bit.

I2C Update Sequence

The MPQ7920 requires a start condition, a valid

I2C address, a register address byte, and a data

byte for a single data update. After receiving

each byte, the MPQ7920 acknowledges the byte

by pulling the SDA line low during the high period

of a single clock pulse. A valid I2C address

selects the MPQ7920. The MPQ7920 performs

an update on the falling edge of the LSB byte.

Figure 13, Figure 14, and Figure 15 show

examples of I2C write and read sequences.

Slave Address

Write Data

8 bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

Wr (Write) = 0

Rd (Read) = 1

Figure 13: I2C Write Example

– Write Single Register

S Slave Address

A Register Address K

Write Data K

A Write Data K+1 A

Write Data K+N

Multi-byte write executed from current register

location (the read-only register will be skipped)

8 bits

Master to Slave

Slave to Master

A = Acknowledge (SDA = Low)

S = Start Condition

P = Stop Condition

NA = Not Acknowledge (SDA = High)

Wr (Write) = 0

Rd (Read) = 1

Figure 14: I2C Write Example

– Write Multi-Register

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