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MPQ7920 Datasheet(PDF) 34 Page - Monolithic Power Systems |
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MPQ7920 Datasheet(HTML) 34 Page - Monolithic Power Systems |
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34 / 44 page ![]() MPQ7920 – 5V POWER MANAGEMENT IC WITH I2C AND MTP, AEC-Q100 MPQ7920 Rev. 1.0 www.MonolithicPower.com 34 7/13/2020 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2020 MPS. All Rights Reserved. Table 1: Output Reference Voltage Chart (Used for 12.5mV DVS Resolution) (continued) D[7:0] VREF (mV) D[7:0] VREF (mV) D[7:0] VREF (mV) 01010000 1400 10100110 2475 11111100 3550 01010001 1412.5 10100111 2487.5 11111101 3562.5 01010010 1425 10101000 2500 11111110 3575 01010011 1437.5 10101001 2512.5 11111111 3587.5 01010100 1450 10101010 2525 N/A N/A 01010101 1462.5 10101011 2537.5 N/A N/A I2C Bus Slave Address The slave address is a 7-bit address followed by an 8th read or write (R/W) data direction bit. The A5 to A1 bits can be configured by the MTP e-Fuse. A7 A6 A5 A4 A3 A2 A1 Setting Value 1 1 0* 1* 0* 0* 1* Notes: 13) This bit is configurable by the MTP e-fuse. 14) By default, the slave address is 0x69, A[7:1] = 110 1001. |
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