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TMP468 Datasheet(PDF) 14 Page - Texas Instruments |
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TMP468 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 49 page ![]() 1 9 1 9 ACK by Device Start by Master R/W 0 1 A0 1 0 A1 P7 P6 P5 P4 P3 P2 P1 P0 ACK by Device Frame 1 Serial Bus Address Byte from Master Frame 2 Pointer Byte from Master 0 D7 D6 D5 D4 D3 D2 D1 D0 1 9 ACK by Device Stop by Master 1 9 D15 D14 D13 D12 D11 D10 D9 D8 ACK by Device Frame 3 Word MSB from Master Frame 4 Word LSB from Master SCL (continued) SDA (continued) SCL SDA 1 9 1 9 ACK by Device Start by Master SCL SDA R/W 0 1 A0 1 0 A1 ACK by Device Frame 1 Serial Bus Address Byte from Master Frame 2 Pointer Byte from Master P7 P6 P5 P4 P3 P2 P1 P0 0 Stop by Master 14 TMP468 SBOS762B – NOVEMBER 2016 – REVISED JUNE 2017 www.ti.com Product Folder Links: TMP468 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Programming (continued) 7.5.1.2 Bus Definitions The TMP468 device has a two-wire interface that is compatible with the I2C or SMBus interface. Figure 15 through Figure 20 illustrate the timing for various operations on the TMP468 device. The bus definitions are as follows: Bus Idle: Both SDA and SCL lines remain high. Start Data Transfer: A change in the state of the SDA line (from high to low) when the SCL line is high defines a start condition. Each data transfer initiates with a start condition. Stop Data Transfer: A change in the state of the SDA line (from low to high) when the SCL line is high defines a stop condition. Each data transfer terminates with a repeated start or stop condition. Data Transfer: The number of data bytes transferred between a start and stop condition is not limited and is determined by the master device. The receiver acknowledges the data transfer. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup and hold times into account. On a master receive, data transfer termination can be signaled by the master generating a not-acknowledge on the last byte that is transmitted by the slave. Figure 15. Two-Wire Timing Diagram for Write Pointer Byte Figure 16. Two-Wire Timing Diagram for Write Pointer Byte and Value Word |
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