Internal Clock

When using the internal oscillator, the capacitance (COSC)

on CLK determines the oscillator frequency:

OSC

OSC

k

f

(kHz)

C

(pF)

=

where

k=87x103 for the

MAX7418/MAX7421/MAX7422/MAX7425

and

k=110X103 for the

MAX7419/MAX7420/MAX7423/ MAX7424.

Since COSC is in the low picofarads, minimize the stray

capacitance at CLK so that it does not affect the inter-

nal oscillator frequency. Varying the rate of the internal

oscillator adjusts the filter’s corner frequency by a 100:1

clock-to-corner frequency ratio. For example, an internal

oscillator frequency of 2.2MHz produces a nominal corner

frequency of 22kHz.

Input Impedance vs. Clock Frequencies

The MAX7418–MAX7425s’ input impedance is effectively

that of a switched-capacitor resistor (see the following

equation), and is inversely proportional to frequency.

The input impedance values determined by the equation

represent the average input impedance, since the input

current is not continuous. As a rule, use a driver with

an output resistance less than 10% of the filter’s input

impedance.

Estimate the input impedance of the filter by using the

following formula:

IN

CLK

IN

1

Z

(f

C )

=

×

where fCLK = clock frequency and CIN = 1pF.

Low-Power Shutdown Mode

The MAX7418–MAX7425 have a shutdown mode that is

activated by driving SHDN low. In shutdown mode, the

filter supply current reduces to 0.2μA, and the output of

the filter becomes high impedance. For normal operation,

drive SHDN high or connect to VDD.

Applications Information

Offset (OS) and Common-Mode (COM)

Input Adjustment

COM sets the common-mode input voltage and is biased

at midsupply with an internal resistor-divider. If the appli-

cation does not require offset adjustment, connect OS

to COM. For applications in which offset adjustment

is required, apply an external bias voltage through a

resistor-divider network to OS, as shown in Figure 4. For

applications that require DC level shifting, adjust OS with

respect to COM. (

Note: Do not leave OS unconnected.)

The output voltage is represented by these equations:

OUT

IN

COM

OS

DD

COM

V

( V

V

) V

V

V

( typical)

2

=

−+

=

where (VIN - VCOM) is lowpass filtered by the SCF and

OS is added at the output stage. See the Electrical

Figure 3. Bessel vs. Butterworth Filter Response

Figure 4. Offset Adjustment Circuit

www.analog.com

Analog Devices │ 11

MAX7418–MAX7425

5th-Order, Lowpass,

Switched-Capacitor Filters

A

2V/div

2V/div

2V/div

C

A: 1kHz INPUT SIGNAL

B: MAX7419 BESSEL FILTER RESPONSE; fC = 5kHz

C: MAX7420 BUTTERWORTH FILTER RESPONSE; fC = 5kHz

B

200µs/div

VDD

VSUPPLY

IN

CLK

GND

INPUT

OUTPUT

50k

50k

50k

OUT

0.1µF

0.1µF

0.1µF

CLOCK

SHDN

COM

OS

MAX7418–

MAX7425