C8051F310 datasheet(103/228 Pages) SILABS

103 / 228 page

Rev. 1.7

103

C8051F310/1/2/3/4/5/6/7

8.4.2. Stop Mode

Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-

tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher-

als are stopped; the state of the external oscillator circuit is not affected. Each analog peripheral (including

the external oscillator circuit) may be shut down individually prior to entering Stop Mode. Stop mode can

only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset

sequence and begins program execution at address 0x0000.

If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.

The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the

MCD timeout of 100 µsec.

SFR Definition 8.12. PCON: Power Control

Bits7–2: GF5–GF0: General Purpose Flags 5–0.

These are general purpose flags for use under software control.

Bit1:

STOP: Stop Mode Select.

Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0.

1: CPU goes into Stop mode (internal oscillator stopped).

Bit0:

IDLE: Idle Mode Select.

Setting this bit will place the CIP-51 in Idle mode. This bit will always be read as 0.

1: CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial

Ports, and Analog Peripherals are still active.)

R/W

Reset Value

GF5

GF4

GF3

GF2

GF1

GF0

STOP

IDLE

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0x87

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