C8051F310 datasheet(115/228 Pages) SILABS

115 / 228 page

Rev. 1.7

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C8051F310/1/2/3/4/5/6/7

10.4. Flash Write and Erase Guidelines

Any system which contains routines which write or erase Flash memory from software involves some risk

that the write or erase routines will execute unintentionally if the CPU is operating outside its specified

operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-

fying code can result in alteration of Flash memory contents causing a system failure that is only recover-

able by re-Flashing the code in the device.

The following guidelines are recommended for any system that contains routines which write or erase

Flash from code.

10.4.1. VDD Maintenance and the VDD Monitor

If the system power supply is subject to voltage or current "spikes," add sufficient transient

protection devices to the power supply to ensure that the supply voltages listed in the Absolute

Maximum Ratings table are not exceeded.

Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot

meet this rise time specification, then add an external VDD brownout circuit to the RST pin of

the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD

drops below 2.7 V.

Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code

as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-

based systems, this will involve modifying the startup code added by the 'C' compiler. See your

compiler documentation for more details. Make certain that there are no delays in software

between enabling the VDD monitor and enabling the VDD monitor as a reset source. Code

examples showing this can be found in "AN201: Writing to Flash from Firmware", available

from the Silicon Laboratories web site.

As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a

reset source inside the functions that write and erase Flash memory. The VDD monitor enable

instructions should be placed just after the instruction to set PSWE to a '1', but before the

Flash write or erase operation instruction.

Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment

operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-

ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.

Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas

to check are initialization code which enables other reset sources, such as the Missing Clock

Detector or Comparator, for example, and instructions which force a Software Reset. A global

search on "RSTSRC" can quickly verify this.

10.4.2. PSWE Maintenance

Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There

should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one rou-

tine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.

Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address

updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code

examples showing this can be found in AN201, "Writing to Flash from Firmware", available

from the Silicon Laboratories web site.

Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has

been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-

viced in priority order after the Flash operation has been completed and interrupts have been

re-enabled by software.

C8051F310 Datasheet(PDF) 115 Page - Silicon Laboratories

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