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C8051F310 Datasheet(PDF) 122 Page - Silicon Laboratories |
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C8051F310 Datasheet(HTML) 122 Page - Silicon Laboratories |
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122 / 228 page ![]() C8051F310/1/2/3/4/5/6/7 122 Rev. 1.7 SFR Definition 12.1. OSCICL: Internal Oscillator Calibration SFR Definition 12.2. OSCICN: Internal Oscillator Control Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6–0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. This reset value for OSCICL deter- mines the oscillator base frequency. The reset value is factory calibrated to generate an internal oscillator frequency of 24.5 MHz. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB3 Bit7: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. Bit6: IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal Oscillator is not running at programmed frequency. 1: Internal Oscillator is running at programmed frequency. Bits5–2: UNUSED. Read = 0000b, Write = don't care. Bits1–0: IFCN1-0: Internal Oscillator Frequency Control Bits. 00: SYSCLK derived from Internal Oscillator divided by 8. 01: SYSCLK derived from Internal Oscillator divided by 4. 10: SYSCLK derived from Internal Oscillator divided by 2. 11: SYSCLK derived from Internal Oscillator divided by 1. R/W R R/W R/W R/W R/W R/W R/W Reset Value IOSCEN IFRDY IFCN1 IFCN0 11000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xB2 |
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