C8051F310 datasheet(189/228 Pages) SILABS

189 / 228 page

Rev. 1.7

189

C8051F310/1/2/3/4/5/6/7

17.1.2. Mode 1: 16-bit Counter/Timer

Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The

counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.

17.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload

Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start

value. TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all

ones to 0x00, the timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If

Timer 0 interrupts are enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is

not changed. TL0 must be initialized to the desired value before enabling the timer for the first count to be

correct. When in Mode 2, Timer 1 operates identically to Timer 0.

Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the

TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0

is active as defined by bit IN0PL in register IT01CF (see Section “8.3.2. External Interrupts” on page 95

for details on the external input signals /INT0 and /INT1).

Figure 17.2. T0 Mode 2 Block Diagram

TCLK

TMOD

TF0

TR0

TR1

TF1

IE1

IT1

IE0

IT0

Interrupt

TL0

(8 bits)

Reload

TH0

(8 bits)

SYSCLK

Pre-scaled Clock

INT01CF

TR0

GATE0

IN0PL

XOR

/INT0

Crossbar

CKCON

C8051F310 Datasheet(PDF) 189 Page - Silicon Laboratories

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