C8051F310 datasheet(196/228 Pages) SILABS

196 / 228 page

C8051F310/1/2/3/4/5/6/7

196

Rev. 1.7

17.2.2. 8-bit Timers with Auto-Reload

When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper-

ate in auto-reload mode as shown in Figure 17.5. TMR2RLL holds the reload value for TMR2L; TMR2RLH

holds the reload value for TMR2H. The TR2 bit in TMR2CN handles the run control TMR2H. TMR2L is

always running when configured for 8-bit Mode.

Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock

source divided by 8. The Timer 2 Clock Select bits (T2MH and T2ML in CKCON) select either SYSCLK or

the clock defined by the Timer 2 External Clock Select bit (T2XCLK in TMR2CN), as follows:

Note: External clock divided by 8 is synchronized with the system clock, and the external clock must be

less than or equal to the system clock to operate in this mode.

The TF2H bit is set when TMR2H overflows from 0xFF to 0x00; the TF2L bit is set when TMR2L overflows

from 0xFF to 0x00. When Timer 2 interrupts are enabled (IE.5), an interrupt is generated each time

TMR2H overflows. If Timer 2 interrupts are enabled and TF2LEN (TMR2CN.5) is set, an interrupt is gener-

ated each time either TMR2L or TMR2H overflows. When TF2LEN is enabled, software must check the

TF2H and TF2L flags to determine the source of the Timer 2 interrupt. The TF2H and TF2L interrupt flags

are not cleared by hardware and must be manually cleared by software.

Figure 17.5. Timer 2 8-Bit Mode Block Diagram

T2MH

T2XCLK

TMR2H Clock

Source

T2ML

T2XCLK

TMR2L Clock

Source

SYSCLK/12

External Clock/8

SYSCLK

TCLK

TR2

External Clock / 8

SYSCLK / 12

T2XCLK

TMR2H

TMR2RLH

Reload

TCLK

TMR2L

TMR2RLL

Interrupt

T2SPLIT

TF2LEN

TF2L

TF2H

T2XCLK

TR2

To ADC,

SMBus

To SMBus

CKCON

C8051F310 Datasheet(PDF) 196 Page - Silicon Laboratories

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