C8051F310 datasheet(200/228 Pages) SILABS

200 / 228 page

C8051F310/1/2/3/4/5/6/7

200

Rev. 1.7

17.3.2. 8-bit Timers with Auto-Reload

When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper-

ate in auto-reload mode as shown in Figure 17.5. TMR3RLL holds the reload value for TMR3L; TMR3RLH

holds the reload value for TMR3H. The TR3 bit in TMR3CN handles the run control TMR3H. TMR3L is

always running when configured for 8-bit Mode.

Each 8-bit timer may be configured to use SYSCLK, SYSCLK divided by 12, or the external oscillator clock

source divided by 8. The Timer 3 Clock Select bits (T3MH and T3ML in CKCON) select either SYSCLK or

the clock defined by the Timer 3 External Clock Select bit (T3XCLK in TMR3CN), as follows:

Note: External clock divided by 8 is synchronized with the system clock, and the external clock must be

less than or equal to the system clock to operate in this mode.

The TF3H bit is set when TMR3H overflows from 0xFF to 0x00; the TF3L bit is set when TMR3L overflows

from 0xFF to 0x00. When Timer 3 interrupts are enabled, an interrupt is generated each time TMR3H over-

flows. If Timer 3 interrupts are enabled and TF3LEN (TMR3CN.5) is set, an interrupt is generated each

time either TMR3L or TMR3H overflows. When TF3LEN is enabled, software must check the TF3H and

TF3L flags to determine the source of the Timer 3 interrupt. The TF3H and TF3L interrupt flags are not

cleared by hardware and must be manually cleared by software.

Figure 17.7. Timer 3 8-Bit Mode Block Diagram

T3MH

T3XCLK

TMR3H Clock

Source

T3ML

T3XCLK

TMR3L Clock

Source

SYSCLK/12

External Clock/8

SYSCLK

TCLK

TR3

External Clock / 8

SYSCLK / 12

T3XCLK

TMR3H

TMR3RLH

Reload

TCLK

TMR3L

TMR3RLL

Interrupt

T3SPLIT

TF3LEN

TF3L

TF3H

T3XCLK

TR3

To ADC

CKCON

C8051F310 Datasheet(PDF) 200 Page - Silicon Laboratories

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