C8051F310 datasheet(204/228 Pages) SILABS

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C8051F310/1/2/3/4/5/6/7

204

Rev. 1.7

18.1. PCA Counter/Timer

The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte

(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches

the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.

Reading the PCA0L Register first guarantees an accurate reading of the entire 16-bit PCA0 counter.

Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2-CPS0 bits in the PCA0MD

source divided by 8’ mode, the external oscillator source is synchronized with the system clock,

and must have a frequency less than or equal to the system clock.

When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is

set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in

PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically

cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-

ware (Note: PCA0 interrupts must be globally enabled before CF interrupts are recognized. PCA0 inter-

rupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit in EIE1 to logic 1). Clearing the

CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the CPU is in Idle

mode.

Figure 18.2. PCA Counter/Timer Block Diagram

Table 18.1. PCA Timebase Input Options

CPS2

CPS1

CPS0

Timebase

System clock divided by 12

System clock divided by 4

Timer 0 overflow

High-to-low transitions on ECI (max rate = system clock divided by 4)

System clock

External oscillator source divided by 8*

*Note:

External oscillator source divided by 8 is synchronized with the system clock.

PCA0CN

PCA0MD

IDLE

PCA0H

PCA0L

Snapshot

To SFR Bus

Overflow

To PCA Interrupt System

PCA0L

read

To PCA Modules

SYSCLK/12

SYSCLK/4

Timer 0 Overflow

ECI

000

001

010

011

100

101

SYSCLK

External Clock/8

C8051F310 Datasheet(PDF) 204 Page - Silicon Laboratories

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