DA7212 datasheet(57/136 Pages) RENESAS

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Ultra-Low Power Stereo Codec

DA7212 Revision 3.6

Nov 1, 2024

CFR011-120-00

Page 57

13.27 SRM PLL Mode (DAI Slave)

SRM mode enables the PLL output clock to be synchronized to the incoming WCLK signal on the DAI. The SRM

PLL mode is enabled by setting the PLL as for normal PLL mode and asserting register bit PLL_SRM_EN.

When using the digital audio interface in Slave mode with the SRM enabled, removing and re-applying the DAI

interface word clock WCLK may cause the PLL lock to be lost. To re-lock the PLL it is recommended that you

disable the SRM (PLL_SRM_EN = 0), reset the PLL by re-writing to register PLL_INTEGER, and then re-enable

the SRM (PLL_SRM_EN = 1) after the DAI WCLK is reapplied.

When switching sample rates between 44.1 kHz and 48 kHz (or between the multiples of these sample rates),

SRM must be disabled and then re enabled using register bit PLL_SRM_EN.

13.28 32 kHz PLL Mode (DAI Master)

32 kHz mode enables the PLL output clock to be synchronized to a 32.768 kHz clock signal on the MCLK pin.

32 kHz PLL mode is selected by enabling the PLL and asserting both PLL_SRM_EN and PLL_32K_MODE.

13.29 Operating with a 2 MHz to 5 MHz MCLK

When using the PLL with a 2 MHz-5 MHz MCLK, you must follow the procedure below to setup the PLL in the

correct mode.

Setup PLL and clocking

Write F0 = 8b

Write F2 = 03

Write F0 = 00

When returning from this mode to a mode with an MCLK >5 MHz, you must follow the procedure below.

Write F0 = 8b

Write F2 = 01

Write F0 = 00

Setup PLL and clocking

13.30 Mixed Sample Rates

In DA7212 there is only one Sample Rate register and therefore, by default, this controls the sample rate of both

the ADC and the DAC.

Some applications require the ADC and the DAC to run at different sample rates. A special mode (24-48 Mode)

is available by asserting 24_48_MODE at register address 0x84[0]. Asserting this bit sets the ADC to run at

24 kHz and the DAC to run at 48 kHz. In this mode all the functionality of the ADC and the DAC is available. The

DAI will continue to run at 48 kHz, and every ADC sample will be repeated across two WCLK frames.

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