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LXT9782 Datasheet(PDF) 23 Page - Intel Corporation |
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LXT9782 Datasheet(HTML) 23 Page - Intel Corporation |
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23 / 78 page ![]() Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782 Datasheet 23 MII Addressing The protocol allows one controller to communicate with multiple LXT97x2 chips. Pins ADD_<4:0> determine the base address. Each port adds its port number (0 through n) to the base address to obtain its port address as shown in Figure 6. Figure 6. Port Address Scheme Figure 7. Management Interface Read Frame Structure BASE ADDR (ex. ADDR=4) PHY ADDR (BASE+0) PHY ADDR (BASE+1) PHY ADDR (BASE+2) PHY ADDR (BASE+3) PHY ADDR (BASE+4) PHY ADDR (BASE+5) ex. 4 ex. 5 ex. 6 ex. 7 ex. 8 ex. 9 LXT9782 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 PHY ADDR (BASE+6) PHY ADDR (BASE+7) ex. 10 ex. 11 Port 6 Port 7 1. Ports 6 and 7 not available on the LXT9762. MDC MDIO (Read) 32 "1"s 01 10 Preamble ST Op Code PHY Address Turn Around Z0 A4 A3 A0 R4 R3 R0 Register Address D15 D14 D1 Data Write Read D15 D14 D1 D0 Idle High Z |
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