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LXT9782 Datasheet(PDF) 33 Page - Intel Corporation

Part # LXT9782
Description  Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII
PDF  78 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

LXT9782 Datasheet(HTML) 33 Page - Intel Corporation

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Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782
Datasheet
33
2.6.5
Loopback
A test loopback function is available for 100 Mbps SMII testing. Bit 0.14 must be set High for
correct operation. When data is looped back, whatever the MAC transmits is looped back in its
entirety, including the preamble. In FX mode, the respective SD/TPn pin must be pulled High to
enable loopback.
2.6.6
Collision
The SMII interface does not provide a collision output and relies on the MAC to interpret COL
conditions using CRS and TX_EN. CRS is unaffected by the transmit path.
Figure 16. Loopback Paths
Digital
Block
SMII
TX Driver
100X
Loopback
FX Driver
Analog
Block
LXT97x2
Figure 17. Serial MII Receive Synchronization
Table 11. RX Status Encoding Bit Definitions
Signal
Definition
CRS
Carrier Sense - identical to MII, except that it is not an asynchronous signal.
RX_DV
Receive Data Valid - identical to MII. When RX_DV = 0, status information is
transmitted to the MAC. When RX_DV = 1, received data is transmitted to the
MAC.
0 = Status Byte
1 = Valid Data Byte
RX_ER
(RXD0)
Inter-frame status bit RXD0 indicates whether or not the PHY detected an error
somewhere in the previous frame.
0 = No Error
1 = Error
SPEED
(RXD1)
Inter-frame status bit RXD1 indicates port operating speed.
0 = 10Mbps
1 = 100Mbps
DUPLEX
(RXD2)
Inter-frame status bit RXD2 indicates port duplex condition.
0 = Half
1 = Full
1. Both RXD0 and RXD5 bits are valid in the segment immediately following a frame, and remain valid until the first data
segment of the next frame begins.
CRS
RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
CRS
CLOCK
SYNC
RX
RXER
Speed
Duplex
Link
Jabber
Valid
RXD6
RXD7



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