LXT9782 datasheet(32/78 Pages) INTEL

32 / 78 page

LXT9762/9782 — Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII

Datasheet

2.6.4

Receive Data Stream

Receive data and control information are signalled in ten bit segments. In 100 Mbps mode each

segment contains a new byte of data. In 10 Mbps mode each segment is repeated ten times (except

for the CRS bit) and the MAC can sample any one of the ten segments.

2.6.4.1

Carrier Sense

The CRS bit (slot 0) is generated when a packet is received from the network interface. The CRS

bit is set in real time, even in 10 Mbps mode. (All other bits are repeated in 10 sequential

segments).

2.6.4.2

Receive Data Valid

The LXT97x2 asserts the RX_DV bit (slot 1) when it receives a valid packet. The assertion timing

changes depend on line operating speed:

• For 100TX and 100FX links, the RX_DV bit is asserted from the first nibble of preamble to

the last nibble of the data packet.

• For 10BT links, the entire preamble is truncated. The RX_DV bit is asserted with the first

nibble of the Start-of-Frame Delimiter (SFD) “5D” and remains asserted until the end of the

packet.

2.6.4.3

Receive Error

In 100BASE-X mode when the LXT97x2 receives an errored symbol from the network, it drives

“1110” on the associated RXD pin.

2.6.4.4

Receive Status Encoding

The LXT97x2 encodes status information onto the RXD line during IPG as listed in Table 11 on

page 33. Status bit RXD<5> indicates the validity of the upper nibble (RXD<7:4> of the last byte

of the previous frame). RXD and RX_DV are passed through the internal elasticity FIFO to

smooth any clock rate differences between the recovered clock and the 125 MHz reference clock.

Figure 15. Serial MII Transmit Synchronization

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

CLOCK

SYNC

TX_EN

TX_ER

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