LXT9782 datasheet(5/78 Pages) INTEL

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Datasheet

Fast Ethernet 10/100 Multi-Port Transceiver with Serial MII — LXT9762/9782

Figures

LXT 9782 Block Diagram ...................................................................................... 9

LXT9782HC (PQFP) Preliminary Pin Assignments............................................10

LXT9782BC (PBGA) Preliminary Pin Assignments............................................11

LXT9762HC (PQFP) Preliminary Pin Assignments ............................................12

LXT97x2 Interfaces ............................................................................................ 21

Port Address Scheme .........................................................................................23

Management Interface Read Frame Structure ................................................... 23

Management Interface Write Frame Structure ................................................... 24

Interrupt Logic .................................................................................................... 24

Initialization Sequence ....................................................................................... 26

Hardware Control Settings ................................................................................. 27

Link Establishment Process ............................................................................... 29

Simplified SMII Application Diagram .................................................................. 30

100Mbps Serial MII Data Flow ........................................................................... 31

Serial MII Transmit Synchronization .................................................................. 32

Loopback Paths................................................................................................... 33

Serial MII Receive Synchronization .................................................................... 33

100BASE-X Frame Format ............................................................................... 34

Protocol Sublayers ............................................................................................. 36

Serial LED Streams............................................................................................. 42

LED Pulse Stretching .......................................................................................... 43

Quick Status Register.......................................................................................... 44

Power and Ground Supply Connections ............................................................ 49

Typical Twisted-Pair Interface ............................................................................50

Typical Fiber Interface ........................................................................................ 51

Typical Serial LED Interface................................................................................ 52

MII Sync Timing................................................................................................... 56

100BASE-TX Receive Timing ............................................................................. 56

SMII Output Delay Test Setup............................................................................57

100BASE-TX Transmit Timing ............................................................................57

100BASE-FX Receive Timing ............................................................................. 58

100BASE-FX Transmit Timing ............................................................................58

10BASE-T Receive Timing..................................................................................59

10BASE-T Transmit Timing................................................................................. 59

Auto-Negotiation and Fast Link Pulse Timing .................................................... 60

Fast Link Pulse Timing ....................................................................................... 60

MDIO Write Timing (MDIO Sourced by MAC) .................................................... 61

MDIO Read Timing (MDIO Sourced by PHY) .................................................... 61

Power-Up Timing ................................................................................................ 62

Reset and Power-Down Recovery Timing ......................................................... 62

PHY Identifier Bit Mapping ..................................................................................68

LXT97x2 PQFP Package Specification...............................................................77

LXT97x2 PBGA Package Specification...............................................................78

LXT9782 Datasheet(PDF) 5 Page - Intel Corporation

LXT9782 Datasheet(HTML) 5 Page - Intel Corporation

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